Xilinx Error: Place 1018 解决方案
本人FPGA新手一枚，近期在用Xilinx_ISE_DS_Win_12.4学习Xilinx芯片。
现FPGA有3路信号inputA,inputB,inputZ,我想用数组记录这3路信号前30次不同的电平信息，然后在CPU中通过通讯将这些数据读出来。
我所编写的VHDL程序如下：
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type uvwData is array(30 downto 0) of std_logic_vector(7 downto 0); signal uvwArray:uvwData; signal inputA_temp,inputB_temp,inputZ_temp:std_logic; signal buff_uvw: std_logic_vector(7 downto 0); signal uvw_val:std_logic_vector(7 downto 0); process(inputA, inputB, inputZ,reset1) variable uvwCount: integer range 0 to 30; begin if reset1='1' then for i in 0 to 30 loop uvwArray(i)<="11111111"; end loop; uvwCount := 0; else buff_uvw <= inputA&inputB&inputZ&'0'&'0'&'0'&'0'&'0'; if buff_uvw /= uvw_val then if uvwCount < 30 then --有此赋值语句时，编译就会有错；删除此语句编译即可通过 uvwArray(uvwCount) <= buff_uvw; uvwCount := uvwCount + 1; uvw_val <= buff_uvw; end if; end if; end if; end process; |
编译所报的错误信息如下：
ERROR:Place:1018 – A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <outputZ_c_0_not0000_BUFG> is placed at site <BUFGMUX_X1Y1>. The IO component <reset> is placed at site <PAD187>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET “reset” CLOCK_DEDICATED_ROUTE = FALSE; >
从实验现象上分析，我一直以为我数组赋值的方式不对，不然为什么加了”uvwArray(uvwCount) <= buff_uvw;“就编译出错呢？我从数组赋值的角度出发找了很久，但各种资料显示我这样用数组应该是对的。
推翻数组使用问题这个猜测后，针对这个错误我找到了两种解决方案：
方案1：我先尝试了按照错误信息的提示来解决问题。从错误信息来看，在.ucf文件中添加“NET “reset” CLOCK_DEDICATED_ROUTE = FALSE;”可以解决问题，验证后这个方案确实可以让编译顺利通过；
方案2：我搜索关键词ERROR:Place:1018，在http://stackoverflow.com/questions/7589443/xilinx-error-place-1018-message看到相关内容，原来这就是FPGA中传说的同步复位与异步复位的问题。按照该方案修改程序后，程序也可以顺利通过编译。根据该链接中的说法，第1种方案是不可取的，我们通常应该用如下结构来编写VHDL程序：
异步复位程序结构：
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process (clk, reset) begin if reset = '1' then -- async reset stuff elsif rising_edge(clk) then -- sync stuff end if; end process; |
同步复位程序结构：
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process (clk) begin if reset = '1' then --sync reset stuff else -- other sync stuff end if; end process; |
我又继续学习关于FPGA的同步复位与异步复位的问题，找到了一份资料《设计与验证:Verilog HDL》，该书中的4.3.9章节详细讲述了两种复位方式的区别，建议用VHDL编程的同学都拜读一下。
